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Throughput control

Variable Count sample RTL[2]

Input control type①
  • iStall is instantly controlled by iVld and input is hold and processed.
  • oVld and oData is output directly from input
  • de-assert iStall at completion, and receive the next iVld
  • iCnt sets count -1 for each iVld. Same as iData, When iStall is asserted then to hold
  • iStall is when joined to iVld, when pipelineis grouped, take care of combination circuit looping
  • xxxFunc() specified arbitrary processing of data. If there is no processing, then is replaced with iData.
Latency(CLK)0 
    
    module gearIT(iData, iCnt, iVld, iStall, oData, oVld, oStall, reset, clk);
            parameter       W       = 32;
            parameter       D       = 4;

            input   [W-1:0] iData;
            input   [D-1:0] iCnt;   // Count Number - 1
            input           iVld;
            output          iStall;
            output  [W-1:0] oData;
            output          oVld;
            input           oStall;
            input           reset;
            input           clk;
    
            wire            oAlloc  = oVld & !oStall;
            reg     [D-1:0] cnt;    // Incrementer
            wire            fin     = oAlloc & (cnt == iCnt);
    
            always @(posedge clk)
                    if (reset | fin)
                            cnt     <= #1 {D{1'b0}};
                    else
                            cnt     <= #1 cnt + oAlloc;
    
            assign iStall   = iVld & !fin;
    
            assign oData    = xxxFunc(iData);
            assign oVld     = iVld;

    function [W-1:0] xxxFunc;
            input   [W-1:0] data;
            xxxFunc = data;
    endfunction
    endmodule
iVld → oVld伝搬
iVld → iStall伝搬
iStall ← oStall伝搬
Direct Input Gearing 1

Input control type②
  • iStall is instantly controlled by iVld, and input is Hold and processed type
  • oVld and oData is latched first
  • iStall is de-asserted when finished, and next iVld is received.
  • iStall is connected to iVld, so to take care of combination circuit loop at the time of pipelinegrouping.
  • xxxFunc() specified arbitrary processing of data. If there is no processing, then is replaced with iData.
Latency(CLK)0 
    
    module gearIL(iData, iCnt, iVld, iStall, oData, oVld, oStall, reset, clk);
            parameter       W       = 32;
            parameter       D       = 4;

            input   [W-1:0] iData;
            input   [D-1:0] iCnt;   // Count Number - 1
            input           iVld;
            output          iStall;
            output  [W-1:0] oData;
            output          oVld;
            input           oStall;
            input           reset;
            input           clk;
    
            reg             oVld;
            reg     [W-1:0] oData;
            wire            iAlloc  = ~|cntD & iVld;
            wire            oAlloc  = oVld & !oStall;
            reg     [D-1:0] cnt;    // Incrementer
            wire    [D-1:0] cntD;   // Incrementer(Next)
            reg     [D-1:0] num;    // Latched Count Number
            wire    [D-1:0] numD    = iAlloc ? iCnt : num;;
            wire            fin     = oAlloc & (cnt == num);
    
            always @(posedge clk)
                    if (reset) begin
                            oVld    <= #1 1'b0;
                            cnt     <= #1 {D{1'b0}};
                    end
                    else begin
                            oVld    <= #1 |cntD | iVld;
                            cnt     <= #1 cntD;
                    end
    
            always @(posedge clk)
                    num     <= #1 numD;
    
            always @(posedge clk)
                    if (!oStall)
                            oData   <= #1 xxxFunc(iData);
    
            assign cntD     = fin ? {D{1'b0}} : cnt + oAlloc;
    
            assign iStall   = iVld & (cntD != numD) | oStall;

    function [W-1:0] xxxFunc;
            input   [W-1:0] data;
            xxxFunc = data;
    endfunction
    endmodule
iVld → oVld切断
iVld → iStall伝搬
iStall ← oStall伝搬
Direct Input Gearing 2

Output Control type
  • iData, iVld are latched frst and then controlled.
  • Based on the value of iStall at finish, divided into further 2 types.
    • iStall=1： Do not accept iVld. Timing arc isBasic type（SⅠ）equialent（Cut RTL red part）。Unnecessary 1 bubble cycle will occur
    • iStall=0： Accept iVld. Timing arc is はBuffer type（SⅡ） equivalent
  • xxxFunc() arbitrarily process data consequently. If not processed then replace with iData or oData
Latency(CLK)1 
    
    module gearO(iData, iCnt, iVld, iStall, oData, oVld, oStall, reset, clk);
            parameter       W       = 32;
            parameter       D       = 4;

            input   [W-1:0] iData;
            input   [D-1:0] iCnt;   // Count Number - 1
            input           iVld;
            output          iStall;
            output  [W-1:0] oData;
            output          oVld;
            input           oStall;
            input           reset;
            input           clk;
    
            reg     [W-1:0] oData;
            reg             oVld;
            wire            iAlloc  = iVld & !iStall;
            wire            oAlloc  = oVld & !oStall;
            reg     [D-1:0] cnt;    // Decrementer
            wire            fin     = ~|cnt & oAlloc;
    
            always @(posedge clk)
                    if (reset)
                            cnt     <= #1 {D{1'b0}};
                    else
                            cnt     <= #1 iAlloc ? iCnt : cnt - oAlloc;
    
            always @(posedge clk)
                    if (iAlloc)
                            oData   <= #1 xxxFunc(iData);
                    else if (!oStall)
                            oData   <= #1 xxxFunc(oData);
    
            always @(posedge clk)
                    if (reset)
                            oVld    <= #1 1'b0;
                    else if (!oVld | !oStall)
                            oVld    <= #1 |cnt | iVld;
    
            assign iStall   = oVld & !fin;

    function [W-1:0] xxxFunc;
            input   [W-1:0] data;
            xxxFunc = data;
    endfunction
    endmodule
iVld → oVldTruncate
iStall ← oStallTruncate
（SⅠ）
iStall ← oStallPropagate
（SⅡ）
Latched Gearing

Logical circuit design > Pipeline > Throughput Control    Next page（Arbitration）   TOP of this page ▲

[1]
When initiating pipeline once only in several cycles due to condition change, then pipeline operating every cycle is redundant.

Therefore, embed a stage to increase throughput in the pipeline initiator part to keep balance.
[2]
Many other variations can be thought of for throughput control. Refer to the above as just one example.