• Data is divided into referencing local for each stage and referencing global for each pipeline. It is not necessary to explicitly separate each, but many times it is used and divided ^[1] as below.
  • Local data is operated by pipeline, control signal and process data change frequently.
  
  
  • Global data define a particular operation of pipeline and change of parameter is less.
  
  
• On the other hand, to control multiple pipelines, it is essential to use FIFO to absorb the flicker. For example, in order to use the parameter at later stage memory access and parallally FIFO to hold paramater is provided. If the FIFO is sufficiently large in order to provide high capacity for absorbing flicker, then proportionally the cost is also high.


• Such as this, parameter FIFO is a branch of actual process, one problem is that the cost is higher than would be expected. In order to reduce the cost,structural compression of data of pipeline is required.^[2]


• The possibility of usage of correlation information of process in this range (frame and definition) is high. For example, matrix parameter for image frame color space transform is generally constant for target image. Further, addressing of DMA continues increment of pattern. Using such correlation information can be compressed and cost can be reduced.
  • Parameter maintaining constant value in frame, from start of processFIFO is branched^[3]and control the main pipeline using start signal of frame. The maximum number of frames that can be inserted into pipeline length till the stage to where parameter are used corresponds to the depth of the FIFO.
  
  
  • Parameter which has a certain variable pattern, can obtain the output value from the input value of FIFO using pattern ROM or computation equation. For example, like in the below diagram, using FIFO for intial value in lower stage and FIFO for variable point of upper stage, based on counter which changes by the number of output of upper stage FIFO and output of lower stage FIFO, new value is calculated by arithmetic operation.（Accumulator of the diagram）。When there is a big change,（Variable point information is contained in upper stage FIFO）lower stage FIFO is updated. When the interval of change is longer, then the initial value FIFO depth can be small and cost can be reduced.
• In order to reduce the cost that incurs due to large number of parameters one other solution is to use alarge capacity memory in system^[4]Just managing the pointer of FIFO and containing it in memory, approximately∞ fluctution can be absorbed. If there is no problem in memory bandwidth（performance）and the cost for using the memory（interface circuit etc） this can be one option. However, memory write will be newly generated and hence is a demerit due to latency.

Compress Using Easy Operation
Divide into 2 FIFO and transmit parameter control Assume data is almost always +1 or +2, and other than that is to be random value The ratio of random value is about 10%, FIFO depth to be ratio of 1:8 Initialization is specified from prior stage by iNew signal（Can also be controlled by Vlid flag fter reset instead if using iNew）。
Latency(CLK)	1	module compress(iVld, iStall, iNew, iData, oVld, oStall, oData, reset, clk); parameter W = 32; parameter NOP = 2'h0; parameter PLUS1 = 2'h1; parameter PLUS2 = 2'h2; parameter CHANGE = 2'h3; input iVld; output iStall; input iNew; input [W-1:0] iData; output oVld; input oStall; output [W-1:0] oData; input reset; input clk; reg [W-1:0] lData; // Latched Data wire [W-1:0] lData0; // Latched Data + 0 wire [W-1:0] lData1; // Latched Data + 1 wire [W-1:0] lData2; // Latched Data + 2 wire eq0; wire eq1; wire eq2; wire iOpVld; wire iOpStall; reg [1:0] iOpData; // Operation Code wire iItVld; wire iItStall; reg [W-1:0] iItData; // Initial Data wire oOpVld; wire oOpStall; wire [1:0] oOpData; // Operation Code wire oItVld; wire oItStall; wire [W-1:0] oItData; // Initial Data reg [W-1:0] oData; wire iAlloc = iVld & !iStall; wire oAlloc = oVld & !oStall; wire oNew = (oOpData == CHANGE); reg [W-1:0] acc; // Past Data for Comparison always @(posedge clk) if (iAlloc) lData <= #1 iData; assign iStall = iOpStall | iItStall; assign lData0 = lData; assign lData1 = lData + 'd1; assign lData2 = lData + 'd2; assign eq0 = (iData == lData0); assign eq1 = (iData == lData1); assign eq2 = (iData == lData2); assign iOpVld = iVld & !iItStall; assign iItVld = iVld & !iOpStall; // Operation Code always @(iNew or eq0 or eq1 or eq2) casex ({iNew, eq2, eq1, eq0}) 4'b1xxx, 4'b0000: iOpData = CHANGE; 4'b0001: iOpData = NOP; 4'b001x: iOpData = PLUS1; 4'b01xx: iOpData = PLUS2; endcase assign iItData = iData; // Operation FIFO (Depth 2^4, Data Width W bit) fifo #(2, 4) opFifo ( .iVld (iOpVld), .iStall (iOpStall), .iData (iOpData), .oVld (oOpVld), .oStall (oOpStall), .oData (oOpData), .reset (reset), .clk (clk) ); // Initial FIFO (Depth 2^1, Data Width W bit) fifo #(W, 1) itFifo ( .iVld (iItVld), .iStall (iItStall), .iData (iItData), .oVld (oItVld), .oStall (oItStall), .oData (oItData), .reset (reset), .clk (clk) ); // Accumulator always @(posedge clk) if (oAlloc) acc <= #1 oData; // Operation always @(oOpData or oItData or acc) casex (oOpData) NOP: oData = acc; PLUS1: oData = acc + 'd1; PLUS2: oData = acc + 'd2; CHANGE: oData = oItData; endcase assign oOpStall = oStall | !oItVld; assign oItStall = oStall | !oOpVld & !oNew; assign oVld = oOpVld & (!oItStall | !oNew); endmodule
iVld → oVld	truncate
iVld → iStall	propagate
iStall ← oStall	truncate

Logical Circuit Design > Pipeline > Parameter    TOP of this page ▲

[1]
More than expected cost is incurred in maintaining of parameter, so there are times when only an identifier is flowed through the pipeline requiring an indirect reference to SRAM. Like this there are many ways to use parameters to reduce the cost.

[2]
Temporary data which does not change frequently can be used similar to parameter in compressed state. Further, there are times when it is once written to memory and then again used

Write/read of parameter to/from memory can be useful for resume, so there is value in considering this.In order to reduce the load of memory access at the time of resume, need to consider whether to implement run length compression or real compression method.

[3]
Way of flowing operation information through the pipeline is similar to data pass operation of processor. Like Register file→operation→register file pipeline, image is of synchronizing operator and operand.

[4]
When accessing external SDRAM, parameter accesses internal SRAM and not SDRAM at times. The purpose is to avoid bottleneck during parameter access as well as reduce increase of SDRAM bandwidth