• If process time of each stage is taken as tS_n{n=0,1,… N-1}, then maximum throughput of pipeline is 1/max(tS₀, tS₁,… tS_N-1). When tS is all equal, then maximum performance is realized.


• It is necessary to keep the delay of logical stages in between stages and the total of FF setup time to below tS_n（depends on operating frequency). Particularly, to take care of the number of data buses and divide these in a well balanced way in stages.


• Stages can be connected freely for arbitrary types. They are not connected without any order though and queing performance, timing restrictions, as well as restrictions in circuit size must be considered.


• A representative connection example is stated. NormallyBuffer type（S_�U）connectionis used, and depending on conditions, other types may be used.

Primitive type（SO）connection

In order to control Stall,FIFO is placed at the end. Is used when flicker in control is for the time being to be excluded, or controlling RAW device for which cannot handshake. Absorbs starting point flicker in iStall, so need to prepare buffer (normally FIFO) which can contain the number of stages where Stall control is not required. Signal to state the empty condition of above stated stages of buffer need to be prepared, which will control starting point. For example, when busy signal of FIFO(not empty or threshold over）is asserted, then the below is executed. Valid is masked (set to 0) for stages for which Stall control is not required. Stall signal is output to previous stages.

Basic Type（SI）connection

Total pipeline is interlinked to Stall, so comparatively easy to control clock gating or resource sharing. Take care of high load as Stall will initiate selector and FF for each stage.

Buffer type（S�U）connection

Absorption buffer of pipeline length N to absorb the flicker of Stall Delay is accumulated in Stall, hence restrictions on logical stages get severe for upper flow stages. If stages are same, then restrictions more severe than forBasic type（SI）connection.

Bus type（S�V）connection

Buffer type（S�U）is placed at end point so the operation is equivalent to FIFO type. Even though it is FIFO operation, data process is possible due to multiple stages. Valid, Stall both truncate timing arc in this system, but if pipeline length N is big then restrictions on logical stages in this system get more severe. Normally use as N=2

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