• Memory access is essential for synchronization for large scale data. It is used for various input/output data access of pipeline as well as sheltering of intermediate result.


• Local memory or system memory managed internally or externally by pipeline, many times both due to costresourceis are limited, and hence competition control is required. This means that latency greatly changes from condition of other master^[1]SRAM used for FIFO is excluded from this discussion.


• Memory access consists of request control and data control, and further can be divided into read control and write control. when these are expressed as matrix, memory unit is interfaced with 4 pipelines. From the below diagram can see, Read pipeline connects data requests through memory unit, Write pipeline parallelly connects data request from memory unit.


• Memory Interfaceused here and basic connection to pipeline is elaborated here. I/O which represents input/output is as seen from memory unit, and stage signal is as seen from stage.
  
  

  I/O	Interface	Connect pipeline	Stage signal	Remark
  I	memRdReq	Request Read	oVld	Read request
  O	memRdGnt	Request Read	oStall	Read permit
  I	memRdAddr	Request Read	oData	Read Address
  I	memRdStrb	Data Read	iStall	Read execute
  O	memRdAck	Data Read	iVld	Read possible
  O	memRdData	Data Read	iData	Read Data
  I	memWrReq	Request Write	oVld	Write request
  O	memWrGnt	Request Write	oStall	Write permit
  I	memWrAddr	Request Write	oData	Write address
  I	memWrStrb	Data Write	iStall	Write execute
  O	memWrAck	Data Write	iVld	Write possible
  I	memWrData	Data Write	iData	Write data




• In Memory access specification Read and Write request maybe common, or request and data maybe synchronous and many such specifications are there, but basically can cover all using the above 4 interface. However there are times when transform bridge is required.


• below are important cautions that pertain to performance
  • Negate of memRdStrb can lock arbitration inside memory unit, and can degrade extremely memory access performance of oher masters. In order to assert memRdStrb, FIFO^[2][3]which can store data for requests generated is prepared.（Primitive type combinationReference）。
  
  
  • Memory unit needs to synchronize address and data before writing to memory so, FIFO which can absorb flicker is prepared.Combinationis used to synchronize. Normally, memWrReq precedes memWrStrb by quite a bit,（specification which only allows that is also there）、if mutual relativistic delay difference is great then using FIFOflicker cannot be absorbed then chances of performance degradation are high. Must try to control relativistic delay difference to be as small as possible. Especially, when the FIFO for absorbing the flicker of memory unit is shared by other masters, then there maybe a bad influence on other masters also.
  
  
• This can be said for all resource sharing, to determine the depth of FIFO required forsynchronizingparallel pipelines, even if the latency is variable, the value needs to be estimated. In order to obtain maximum performance, need to process structurally latency of ∞ which is unrealistic. Actually need to consider the performance change corresponding to the probability distribution of latency.


• It is general to set burst mode for N data access for 1 request. N which is the number of burst can be variable in many cases, in which case throughput control is embedded into data pipeline.

Read control with FIFO
Pipeline with input as address information and obtaining data output. Address length and data length are both 32bit. Same depth FIFO x 2 are used. One is used as Signaling FIFO with no send/receive of data. Control by FIFO is as follows Difference between number of Address generation (Memory) and number of data read（pipeline, is controlled by FIFO so as not to exceed a constant. Control between read from Memory and Data FIFO isJoining by primitive type control。 Signaling FIFO and data FIFO are same depth so, data of this depth only flows through data pipeline. Thus, there is no Wait in data read from memory. Burst access is not supported.
Latency(CLK)	0	module rdMem( iData, iVld, iStall, oData, oVld, oStall, memAddr, memReq, memGnt, memData, memStrb, memAck, reset, clk); input [31:0] iData; // Address input iVld; output iStall; output [31:0] iData; // Read Data output oVld; input oStall; output [31:0] memAddr; output memReq; input memGnt; input [31:0] memData; output memStrb; input memAck; input reset; input clk; wire vVld, vStall; wire dVld; sig vFifo ( // Virtual FIFO .iVld (iVld & memGnt), .iStall (vStall), .oVld (vVld), .oStall (!dVld | oStall), .reset (reset), .clk (clk) ); fifo dFifo ( // Data FIFO .iData (memData), .iVld (memAck), .iStall (), // NC .oData (oData), .oVld (dVld), .oStall (!vVld | oStall), .reset (reset), .clk (clk) ); assign iStall = vStall | !memGnt; assign oVld = vVld & dVld; assign memReq = iVld & !vStall; assign memAddr = oData; assign memStrb = 1'b1; endmodule
iVld → oVld	Truncate
iStall ← oStall	Truncate
iVld → memReq	Propagate
oVld ← memAck	Truncate

Write control with FIFO
Pipeline with input as address information and obtaining data output. Address length and data length are both 32bit. Same depth FIFO x 4 are used. Two are used as virtual FIFO with no send/receive of data. Control by FIFO is as follows If there is difference in the number of Address generation (Memory) and number of data write (pipeline) then the generation of address is permitted (VA FIFO）. Request is done after data is ready hence relative delay is reduced. If there is difference in the number of Address generation (Memory) and number of data write (memory) then data generation is permitted（VD FIFO）. Data is transmitted after request (Not required if the specification is for data to be transmitted beforehand) Burst access not supported.
Latency(CLK)	0	module wrMem( iAdData, iAdVld, iAdStall, iDtData, iDtVld, iDtStall, memAddr, memReq, memGnt, memData, memStrb, memAck, reset, clk); input [31:0] iAdData; // Address input iAdVld; output iAdStall; input [31:0] iDtData; // Write Data input iDtVld; output iDtStall; output [31:0] memAddr; output memReq; input memGnt; output [31:0] memData; output memStrb; input memAck; input reset; input clk; wire adVld; wire dtVld, dtStall; wire vaVld, vaStall; wire vdVld, vdStall; fifo adFifo ( // Address FIFO .iData (iAdData), .iVld (iAdVld), .iStall (iAdStall), .oData (memAddr), .oVld (adVld), .oStall (!memAdGnt | !vaVld | vdStall), .reset (reset), .clk (clk) ); fifo dtFifo ( // Data FIFO .iData (iDtData), .iVld (iDtVld & !vaStall), .iStall (dtStall), .oData (memData), .oVld (dtVld), .oStall (!memDtAck | vdStall), .reset (reset), .clk (clk) ); sig vaFifo ( // Virtual Address FIFO .iVld (iDtVld & !dtStall), .iStall (vaStall), .oVld (vaVld), .oStall (!memAdGnt | !adVld | vdStall), .reset (reset), .clk (clk) ); sig vdFifo ( // Virtual Data FIFO .iVld (memGnt & adVld & vaVld), .iStall (vdStall), .oVld (vdVld), .oStall (!memAck | !dtVld), .reset (reset), .clk (clk) ); assign iDtStall = dtStall | vaStall; assign memReq = adVld & vaVld & !vdStall; assign memStrb = dtVld & vdVld; endmodule
iVld → oVld	Truncate
iStall ← oStall	Truncate
iVld → memReq	Propagate
oVld ← memAck	Truncate

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[1]
Minimum latency of memory access can be calculated from the structure, but the estimation of maximum latency is difficult. For example, if the rights of using the memory by competing parties are frozen by arbitration, then the maximum latency will be ∞

When memory access is commenced, and care is taken to reduce handshakes to control Stall as much as possible, then latency distribution probability can be examined by the frequency of access and distribution method.

[2]
In order to make the FIFO depth ∞ of a parallel pipeline, pointer only needs to be managed, and FIFO data can be replced in system memory. However there is demerit in excessive access to system memory also.

[3]
In case of Write, branching off same pipeline and processing pipeline divided into address and data and having fixed length, FIFO is not required to synchronize such cases.