Logical circuit design
Inquiry Sitemap Link Tips
Resource Sharing

Resource Sharing Sample RTL

State Machine control
  • Product of 4 variables are calculated using one multiplication unit, so S1 to S3 3 states[3]state machine[4] is used.
  • Generate Stall for Hold of input data till Condition S3
  • Execute handshake of output data at condition S3 Output data to be rounded off to 32bit
  • To truncate timing of iStall, 1 more cycle S(IDLE) is newly created and latch input data.
Latency(CLK)3
    
    module product(
            iData0, iData1, iData2, iData3,
            iVld, iStall,
            oData, oVld, oStall,
            reset, clk);
    
            parameter       W       = 32;

            parameter       S1      = 2'h1,
                            S2      = 2'h2,
                            S3      = 2'h3;
    
            input   [W-1:0] iData0, iData1, iData2, iData3;
            input           iVld;
            output          iStall;
            output  [W-1:0] oData;          // Result
            output          oVld;
            input           oStall;
            input           reset;
            input           clk;
    
            reg     [1:0]   state, stateD;
            wire            Stall   = oVld & oStall;
            reg     [W-1:0] aIn, bIn;
            wire    [W-1:0] yOut;
    
            reg             oVld;
            reg     [W-1:0] oData, oDataD;

            wire            iAlloc  = iVld & !iStall;
            wire            oAlloc  = oVld & !oStall;
    
            assign yOut     = aIn * bIn;  // Mul Resource (32bit clip)
    
            always @(state or Stall or
                    oData or yOut or
                    iVld or iData0 or iData1 or iData2 or iData3) begin

                    stateD  = state;        // Default
                    oDataD  = oData;
                    aIn     = {W{1'bx}};
                    bIn     = {W{1'bx}};

                    if (!Stall)
                            case (state)
                                    S1: if (iVld) begin
                                            stateD             = S2;
                                            {aIn, bIn, oDataD} = {iData0, iData1, yOut};
                                    end
                                    S2: begin
                                            stateD             = S3;
                                            {aIn, bIn, oDataD} = {oData,  iData2, yOut};
                                    end
                                    S3: begin
                                            stateD             = S1;
                                            {aIn, bIn, oDataD} = {oData,  iData3, yOut};
                                    end
                            endcase
            end
    
            always @(posedge clk)
                    if (reset)
                            state   <= #1 S1;
                    else
                            state   <= #1 stateD;
    
            always @(posedge clk)
                    if (reset)
                            oVld    <= #1 1'b0;
                    else
                            oVld    <= #1 (stateD == S3);
    
            always @(posedge clk)
                    oData   <= #1 oDataD;
    
            assign iStall   = iVld & (state != S3) | oStall;
    endmodule
    
            
iVld → oVldtruncate
iVld → iStallpropagate
iStall ← oStalltruncate
State Machine

Logical Design Circuit > Pipeline > Resource Sharing    Next Page(Paramter)   TOP of this page ▲

[1]
Slight difference in trend generated due to priority method, will remain unchanged even if simulation time is increased, so it can be thought that this is only a structural difference. However, due to the flicker of Stall positive aspect and negative aspect reverse is strange, and must be examined carefully.
[2]
Based on the characteristics of pipeline, for memory unit of the same resource, Read→process→Write steps are mostly followed. Consequent Read and Write access increase the efficiency. However, read and write access are separated for accesses that require logical bandwidth.
[3]
Actual state definition is, named so that can know what it performs in detail so that it is easy to understand.
[4]
oAlloc and(state==S2) conditions do not overlap so this expression is used, in the future if it is shrunk and condition becomes only one then will not be able to correspond. Hence as much as possible the it is better to express in a way that considers overlap.