• Each flow of work in a pipeline is called a stage, data is processed from upper to lower.


• Type of stage are divided into 5 primitives and defined.In order to integrate intoCombination ruleit is limited to minimum required primitives.


• Valid data signal is propagated from upper to lower flow and Stall data signal is propagated from lower to upper flow. Valid signal states that data signal is valid to be processed at lower stage. Stall signal states to upper stage that data can no longer be processed.


• Whether to truncate or propagate the timing arc of Valid, Stall signals（Delay bus）at a stage, is an important factor in the consideration of delay performance. Information regarding the timing arc of Valid and Stall signals is stated with truncate and propagate.


• Data process is arbitrary, hence in the sample circuit it is expressed as cloud image and in sample RTL as xxxFunc(). When there is no data process, this workflow is omitted.

Primitive Type（SO）
Data propagation without conditions type Cannot control stop, hence basically cannot use independently. Valid transmit timing is fixed, hence easy to control for resource sharing.
Latency(CLK)	1	module s0(iData, iVld, oData, oVld, reset, clk); parameter W = 32; input [W-1:0] iData; input iVld; output [W-1:0] oData; output oVld; input reset; input clk; reg [W-1:0] oData; reg oVld; always @(posedge clk) oData <= #1 xxxFunc(iData); always @(posedge clk) if (reset) oVld <= #1 1'b0; else oVld <= #1 iVld; function [W-1:0] xxxFunc; input [W-1:0] data; xxxFunc = data; endfunction endmodule
iVld → oVld	truncate
iStall ← oStall	-

Basic Type（S�T）
Basic type Used when broadcast controlling Stall
Latency(CLK)	1	module s1(iData, iVld, iStall, oData, oVld, oStall, reset, clk); parameter W = 32; input [W-1:0] iData; input iVld; output iStall; output [W-1:0] oData; output oVld; input oStall; input reset; input clk; reg [W-1:0] oData; reg oVld; always @(posedge clk) if (!iStall) oData <= #1 xxxFunc(iData); always @(posedge clk) if (reset) oVld <= #1 1'b0; else if (!iStall) oVld <= #1 iVld; assign iStall = oStall; function [W-1:0] xxxFunc; input [W-1:0] data; xxxFunc = data; endfunction endmodule
iVld → oVld	truncate
iStall ← oStall	truncate

Buffer Type（S�U）
Most used normally type When non-activated（Valid=0）、stop later stage Stall propagation so that can utilize queing to later stages. Can absorb(once) flickering of Stall
Latency(CLK)	1	module s2(iData, iVld, iStall, oData, oVld, oStall, reset, clk); parameter W = 32; input [W-1:0] iData; input iVld; output iStall; output [W-1:0] oData; output oVld; input oStall; input reset; input clk; reg [W-1:0] oData; reg oVld; always @(posedge clk) if (!iStall) oData <= #1 xxxFunc(iData); always @(posedge clk) if (reset) oVld <= #1 1'b0; else if (!iStall) oVld <= #1 iVld; assign iStall = oStall & oVld; function [W-1:0] xxxFunc; input [W-1:0] data; xxxFunc = data; endfunction endmodule
iVld → oVld	truncate
iStall ← oStall	propagate

Bus type（S�V）
Buffering according to the condition of later stages type. When blocked from later stages（Stall=1） only, possible to que at this stage. Characteristics are a pair with buffer type and by combining both can get equivalent of FIFO type. Can absorb(once) flickering of Stall
Latency(CLK)	0	module s3(iData, iVld, iStall, oData, oVld, oStall, reset, clk); parameter W = 32; input [W-1:0] iData; input iVld; output iStall; output [W-1:0] oData; output oVld; input oStall; input reset; input clk; reg [W-1:0] tData; reg tVld; always @(posedge clk) if (!tVld) tData <= #1 iData; always @(posedge clk) if (reset) tVld <= #1 1'b0; else tVld <= #1 oVld & oStall; assign iStall = tVld; assign oData = xxxFunc(tVld ? tData : iData); assign oVld = iVld | tVld; function [W-1:0] xxxFunc; input [W-1:0] data; xxxFunc = data; endfunction endmodule
iVld → oVld	propagate
iStall ← oStall	truncate

FIFO type（FIFO[1]）
Buffering according to the condition of later stages type When blocked from later stages or already queued, can que at this stage. Number of queues is arbitrary and is managed using a pointer. When a simple circuit is used for data, then to take care of delay as it is selector output. Absorption of flicker of Stall is possible (as deep as the FIFO) It is commonly used for truncating the timing arc of Valid, Stall by inserting it in between stages as well as adjusting the timing when combining pipelines. Allocate 'full' to iStall, 'not empty' to oVld. Further, there are times when iStall states 'full' meaning that arbitrary threshhold has been exceeded and not that buffer is full. Normally it is the latter though. Often used is FIFO for control of deletion of data port.
Latency(CLK)	1	module fifo(iData, iVld, iStall, oData, oVld, oStall, reset, clk); parameter W = 32; parameter D = 4; input [W-1:0] iData; input iVld; output iStall; output [W-1:0] oData; output oVld; input oStall; input reset; input clk; reg iStall; reg oVld; reg [W-1:0] tData[0:(1<<D)-1]; reg [D:0] iPtr; reg [D:0] oPtr; wire [D:0] iPtrD = iPtr + (iVld & !iStall); wire [D:0] oPtrD = oPtr + (oVld & !oStall); always @(posedge clk) if (iVld & !iStall) tData[iPtr[D-1:0]] <= #1 xxxFunc(iData); always @(posedge clk) if (reset) begin iStall <= #1 1'b0; oVld <= #1 1'b0; iPtr <= #1 {D+1{1'b0}}; oPtr <= #1 {D+1{1'b0}}; end else begin iStall <= #1 (iPtrD[D] != oPtrD[D]) & (iPtrD[D-1:0] == oPtrD[D-1:0]); oVld <= #1 (iPtrD != oPtrD); iPtr <= #1 iPtrD; oPtr <= #1 oPtrD; end assign oData = tData[oPtr[D-1:0]]; function [W-1:0] xxxFunc; input [W-1:0] data; xxxFunc = data; endfunction endmodule
iVld → oVld	truncate
iStall ← oStall	truncate

Logical Circuit Design > Pipeline > Structure of Stage    Next Stage（Stage connection）   Top of this page ▲

[1]
FIFO not just synchronizes between pipelines, but is also convenient for truncating the timing arc in between stages.