• Differing pipelines are processed basically asynchronously, there are also many cases where they need to be synchronous due to arbitration


• When 1 pipeline is branched into multiple pipelines and then later combined into 1 pipeline, the following basically needs caution.
  • Final throughput（Output of Pipeline A, B, C in the example of the diagram）needs to be equal, and the period of synchronization to be same
  • When there is a difference in latency, there is a performance drop by latency ratio due to stall in combination control, ad so to match to maximum latency as much as possible. When memory access is a variable like latency, FIFO is inserted. In the diagram this is inserted only in Pipeline Cbut there are many cases when it needs to be inserted in A and B also^[1][2]（Maximum latency needs to be ascertained.）
• As in diagram, node 0 of awaiting FIFO B is not locked,（Primitive type（S_O）connectionrefer）,if absorption volume B is insufficient,^[3]then the oppositecombinationNode I vld signal propagation maybe inhibited. Hence synchronization FIFO A is inserted after Node I,latency A is added to latency X and results in opposite effect^[4] Especially take care of data volume increasing due to arbitration of Node I andthroughput control. It is an example ofmemory connection. Of cource it is not for disallowing FIFO for truncating timing arc.


• Process of differing pipelines lead to variation in throughput, but if they are not the same at the time of combination, then need to synchronize at frame unit. Master pipeline for controlling throughput is prepared, and by propagating termination flag to each pipeline, fraction processing is executed for the other pipelines at the time of combination.
  • For pipelines whose termination flag is asserted before the master pipelines, stall control is truncated, and dummy valid vld is generated towards later stages,（data can be Unkown or Copy of end point depending on the specification）
    ⇒ In the below diagram, iStall sent to pipe A_A is an example of truncation, and until all the pipelines are synchronized is on Hold
  
  
  • For pipelines whose termination flag is asserted after the master pipelines, stall control is passed and dummy invalid vld is generated towards later stages（data is normally cut）
    ⇒ In the below diagram, iStall sent to pipe B_B is and example of passing, and until asll the pipelines are synchronized is on deassert(0)
  
  
  • To keep the unmatched interval to a minimum, fram length is kept to equal as much as possible, and to avoid consumption of unnecessary cycles.


• When vld is branched, stall to later stages is combinedWhen used by rules, synergistic effect due to flicker, throughput will drastically fall. Hence must absorb the flicker usingBuffer type（S₂）combinationorFIFO The diagram shows the case where due to random stall generation, later stages are branched into 8 stages and the relation between FIFO depth（X axis） and throughput（Y axis）

Routing
By combination control pipeline 0 by termination flag end. When all pipelines output end then terminate the frame Manage whether the end is early or late from the standard for each pipeline. It is OK to control the condition by measuring the number of each end, （number of FF maybe saved but when number of pipeline is large then logical stages can get very large.） Omit data coding
Latency(CLK)	0	module combine(iVld, iStall, iEnd, oVld, oStall, reset, clk); parameter N = 4; parameter IDLE = 2'h0, PASS = 2'h2, // Late End BLOCK = 2'h3; // Early End input [N-1:0] iVld; output [N-1:0] iStall; input [N-1:0] iEnd; output oVld; input oStall; input reset; input clk; reg [N-1:0] cnd[0:N-1]; // Pipeline Condition reg [N-1:0] cndD[0:N-1]; // Number0 is useless reg [N-1:0] iDummyVld; // Condition = EARLY reg [N-1:0] iDummyStall; // Condition = LATE reg [N-1:0] iDummyVldD; reg [N-1:0] iDummyStallD; wire [N-1:0] iAlloc = iVld & ~iStall & iEnd; wire iDone = &(iAlloc | iDummyStall); wire nasc = &(iVld | iDummyVld) & ~|oStall; integer i; always @(posedge clk) if (reset) for (i=0; i<N; i=i+1) cnd[i] <= #1 IDLE; else for (i=0; i<N; i=i+1) cnd[i] <= #1 cndD[i]; always @( cnd[0] or cnd[1] or cnd[2] or cnd[3] or iAlloc or iDone ) begin for (i=0; i<N; i=i+1) cndD[i] = cnd[i]; // Default Case for (i=0; i<N; i=i+1) case (cnd[i]) IDLE: casex ({iDone, iAlloc[i], iAlloc[0]}) 3'b001: cndD[i] = PASS; 3'b01x: cndD[i] = BLOCK; endcase PASS: casex ({iDone, iAlloc[i]}) 2'b1x: cndD[i] = IDLE; 2'b01: cndD[i] = BLOCK; endcase BLOCK: if (iDone) cndD[i] = IDLE; endcase end always @( cndD[0] or cndD[1] or cndD[2] or cndD[3] ) for (i=0; i<N; i=i+1) begin iDummyVldD[i] = (cndD[i] == PASS); iDummyStallD[i] = (cndD[i] == BLOCK); end always @(posedge clk) if (reset) iDummyVld <= #1 {N{1'b0}}; else for (i=0; i<N; i=i+1) iDummyVld <= #1 iDummyVldD; always @(posedge clk) if (reset) iDummyStall <= #1 {N{1'b0}}; else iDummyStall <= #1 iDummyStallD; assign iStall = iDummyStall | {N{!nasc}}; assign oVld = nasc; endmodule
iVld → oVld	Propagate
iVld → iStall	Propagate
iStall ← oStall	Propagate

Logical Design Circuit > Pipeline > Synchronization    Next Page（Memory connection）   TOP of this page ▲

[1]
Normal to insert in between the front stage of branch of FIFO for synchronization and later stage of combination. However generally, pipelines from other systems run parallelly（sometimes dont know until properly organized) Even in these case insert FIFO before branch and after combination.

[2]
FIFO for synchronization is only for synchronizing other pipelines. Even when at the proper position, capacity shortage occuring, when having proper capacity, wrong positioning, contribute to bottlenecks of performance in large scale system LSI.

[3]
It is difficult to ascertain the depth of FIFO in a variable latency, and sometimes it is a unrealistic value. The approach differs depending upon cost as contrasted to performance, and generally is determined by the designer.

However if quantitative evaluation is lacking, may result in troubles. Hence need to clarify the concept to the system designer regarding cost and performance.

[4]
FIFO A is not definitely bad. When there are multiple node I and need to control simultaneously, then all the Stall of Node I are not '0', then cannot issue so even with slight flicker perfomance will deteriorate. In this case FIFO A is required.