• When dividing complex functions, can divide until pipeline structure. Each function is simple so can optimally design and then by joining these can construct function with high performance Hence a state machine is not definitely required.


• However, state machine can describe condition shift at step unit making excellent readability, thus making changes relatively easier. If condition shift takes performance into account then there is no problem. Hence can be said that there is almost no designing without the use of state machine.


• When there is condition shift then state machine can be easily made, hence our focus will be on creating the condition shift. For instance, if there is to be done an analysis of MPEG headerhwere there is undoubtful sequence^[1]then there will not be many steps generated. However, need to think of bus connection of different protocols, whereby there would be condition shifts depending on the connection conditions.


• Here, will enumerate hints for thinking of condition shifts and description methods for these. There is no correct way, and hence will provide some examples that we thought of as well as techniques.

• We design pipeline as framework for large structures. State machine is usd as a bridge part to sequencer or bus controller at the origin of the pipeline. Hence, depending on the situation, small scale state machine is also used.


• Almost all are small scale state machines at the connection of pipeline, sometimes complex functions need to be implemented. In that case, need to resolve whether to express the function using one condition variable or more than one.


• function expressed by 2 or more condition variables, can be divided and reconnected. Conversely, function expressed only by 1 condition variable looks complex but is actually a simple sequence. LatterFPU program counter can be an example


• When can divide into 2 or more condition variables, there are times when only 1 condition variable is used for expression. It is determined by readability and risk of bug insertion, and there is no definite logical reason. We try to use as less as possible condition variables, and to divide as much as possible.^[2]。


• There are many exceptions. It is seen a lot in sequences which are specified, thereis no merit to dividing conditions that are exclusive. Further, there are times when divided condition is created but joined condition is better.（See example later on.）Need to judge based on the number of connections, and each of the functions.

• First in state machines（hereafter,FSM: Finite State Machine）is Moore（condition is refected in output）or Mealy（input signal and condition is reflected in output） types are present. Difference in type is difference in latency and delay propagation. In normal designing, both may be mixed and it is not necessary to differentiate between the two, however generally Moore type which has the better timing is used as basic.


• Since this is circuit design, will also elaborate on One hot. Generally, it is explicit bit assign（'1' is only 1 set）, decode is unnecessary and is beneficial with regards to speed. However if the state machine is for large scale design, then no need to take undue caution^[3]。
  
  
    Encoded state  

          parameter       IDLE    = 2'h0,
                          DO      = 2'h1,
                          LOOP    = 2'h2,
                          CONT    = 2'h3;
              

  
  One hot state  

        parameter       IDLE    = 4'b0001,
                        DO      = 4'b0010,
                        LOOP    = 4'b0100,
                        CONT    = 4'b1000;
            



• State machine basically interfaces with control signal, hence it is necessary to define it beforehand. If to be designed as a bridge to some part, then many times the control signal is already defined at the connection origin, and there is no need to redefine it.


• Beginning of designit is recommended that optimization of conenction origin is considered (peformance maximization)^[4]In this case, output signal is grouped according to changes. Will also consider if common control signal can be used to operate. Also simultaneously will group input signal according to changes.


• Number of state machine are determined by the output signal groups. For example, for here mentionedBus Protocalcan see clearly that 3 groups consisting of Request, Read Data, Write Data can be divided. When each group operates inasynchronous^[5]then there is further scope of considering division. Message signal is required for connection of state machine.


• Condition is considered for output signal which is grouped. Chart with condition hypthesized is plotted on Y-axis and input signal group on X-axis. Next condition is recorded against change of input signal group.（Same as truth chart）。


• When a new condition is required due to the input signal group（output signal group does not change）, depending on the condition the table is again filled.


• Conditionexpresses output control group, can be output as is. Thus as is, state machine is created based on Moore type.


• Sometimes it is difficult to express complete or part of output signal group only by condition. Mealy type requiring input signal group is such. In this case next condition of the above table is used instead. Need to evaluate if output signal group can be expressed by this next condition


• Even when designed according to specifications, condition shift maynot cover all the condition. Although not required according to specifications, for Fail safe, need to also think of combination of unconsidered condition and input signal group. Ideal isto have a stable condition to return to instead of no condition.^[6]。

• AHB is masterand bus hypothesizedis slave and bus bridge is considered.Specifications for AHB can be referenced separately


• To simplify explanations, will only perform Read（Write Data Bus is omitted.）Further, AHB access control signal HTRANS, address signal HADDR, Acknowledge signal HREADY, Read Data signal HRDATA only will be used.


• For HREADY the logic is opposite, but meaning of pipeline control STALL is same. Input signal group consists of AHB and united slave bus signal^[7] All slave bus signals （req, gnt, strb, ack） are combined.


• Signal is divided into groups. Slave bus req, gnt, addr are as Request signal group, and slave bus strb, ack, flush, data are as Read Data signal group. There is no connection ^[7] between both and hence there is no signal for mutual communication.


• First Request signal group condition shift is determined.
  • Group representing signal req condition can be either '0' or '1', but from slave bus specification need to assert the origin of burst boundary or origin of transaction. Will assume 3 conditions（To differentiate condition name of Read Data side will attach A_）.
    
    

    Condition Name	Explanation
    A_NOP	No access condition
    A_REQN	Origin access condition
    A_REQS	No origin access condition

  
  
  
  • By condition determined temporarily and input signal group , can determine the shift condition. Using the condition of input signal group HREADY and HTRANS, will determine condition shift. Although HTRANS="SEQ" is not permitted for the first access, will shift to condition A_REQ where access can be made. When HREADY='0' or HTRANS="BUSY" then access is pending and a special condition may be required. But have designed so that can easily shift from A_NOP to A_REQ which will be used.（Part in red words.）。
    
    

    Condition name	HREADY	HTRANS	Next condition
    A_NOP	0	x	A_NOP
    	1	IDLE	A_NOP
    		BUSY	A_NOP
    		NONSEQ	A_REQN
    		SEQ	A_REQS
    A_REQN	0	x	A_NOP
    	1	IDLE	A_NOP
    		BUSY	A_NOP
    		NONSEQ	A_REQN
    		SEQ	A_REQS
    A_REQS	0	x	A_NOP
    	1	IDLE	A_NOP
    		BUSY	A_NOP
    		NONSEQ	A_REQN
    		SEQ	A_REQS

    
    
  
  
  • Final condition shift diagram on Request side is as below
• Next will determine Read Data signal group condition shift
  • Group representing signal strb condition can be either '0' or '1', but from slave bus specification need to assert flush at end of burst boundary or end of transaction. Will assume 3 conditions（To differentiate condition name of Read Data side will attach A_）. End of burst boundary, access counter（can replace add signal if using Request of AHB and synchronizing of Data） can be checked, but need to check HTRANS to judge transaction end^[8]. Hence, termination determnation cannot be made until next condition
  
  
  • Current condition is used in strb signal, and next condition is used in flush signal. Next condition can be generated by combining current condition and input signal group. Regarding flush signal, will be Mealy type state machine（Mixed type）。
  
  
  • Finally, in addition to Request and condition specifying origin of same transaction, assume 3 conditions（To differentiate between Request side condition name will attach R_ in front）.Next condition will assert flush signal at R_NOP and R_REQ.
    
    

    Condition name	Explanation
    R_NOP	No access condition
    R_REQN	origin access condition
    R_REQS	no origin access condition

  
  
  
  • By condition determined temporarily and input signal group , can determine the shift condition same as REQ. Need to Stall and Hold strb signal, so when HREADY='0' it is different from Request side. Also even when HTRANS="BUSY" at R_REQN and R_REQS condition, same as for Request cannot shift to R_NOP. If try to shift then Flush signal will mistakenly be asserted.
    
    

    Condition name	HREADY	HTRANS	Next condition
    R_NOP	0	x	R_NOP
    	1	IDLE	R_NOP
    		BUSY	R_NOP
    		NONSEQ	R_REQN
    		SEQ	R_REQS
    R_REQN	0	x	R_REQN
    	1	IDLE	R_NOP
    		BUSY	???
    		NONSEQ	R_REQN
    		SEQ	R_REQS
    R_REQS	0	x	R_REQS
    	1	IDLE	R_NOP
    		BUSY	???
    		NONSEQ	R_REQN
    		SEQ	R_REQS

    
    
  
  
  • Hence empty access condition R_SPC is added. With this can support AHB access termination^[9]。
    
    

    Condition name	HREADY	HTRANS	Next condition
    R_NOP	0	x	R_NOP
    	1	IDLE	R_NOP
    		BUSY	R_NOP
    		NONSEQ	R_REQN
    		SEQ	R_REQS
    R_SPC	0	x	R_SPC
    	1	IDLE	R_NOP
    		BUSY	R_SPC
    		NONSEQ	R_REQN
    		SEQ	R_REQS
    R_REQN	0	x	R_REQN
    	1	IDLE	R_NOP
    		BUSY	R_SPC
    		NONSEQ	R_REQN
    		SEQ	R_REQS
    R_REQS	0	x	R_REQS
    	1	IDLE	R_NOP
    		BUSY	R_SPC
    		NONSEQ	R_REQN
    		SEQ	R_REQS

    
    
  
  
  • Read Data side final condition shift diagram is as follows

• Coding pattern of state machine used here.
  • Condition is defined using parameter word. Will use easily understood condition name
  
  
  • Value of condition, will try to use so that ech bit will have meaning^[10]。
  
  
  • Next condition will be created by replacement word.
  
  
  • At the origin of replacement wordset default value^[11]。
  
  
  • case(condition)word to be upper, case(input signal group)word to be lower（can be vice versa to facilitate understanding）。
  
  
  • each condition, when changing only,next conditionis set.


• Conditionwhen processed and output signal is obtained,next condition also processed and lateched then output signal of FF output is obtained.（Refer to Moving of delay）Selected depending on circuit magnitude and delay situation.


• Next conditionwhen processed and output signal is obtained, connection destination is checked to determine that there is no loop in the circuit. Mutually it occurs when input signal is combined to generate output signal. When there is loop, in generating next conditioninput signals which overlap are cut to create a special next condition


• Bus bridge created using the above, can be coded as below


State machine with 2 conditions（elaborated above）

/* **************************** MODULE PREAMBLE ********************************

        Copyright (c) 2012, ArchiTek
        This document constitutes confidential and proprietary information
        of ArchiTek. All rights reserved.
*/

// ***************************** MODULE HEADER *********************************

module busBridge_0 (
        HTRANS, HADDR, HREADY, HRDATA,
        oReq, oGnt, oAddr, oStrb, oAck, oFlush, oData,
        reset, clk
        );

// ************************ PARAMETER DECLARATIONS *****************************

        parameter               BLR             = 2;

        parameter               A_NOP           = 2'h0,
                                A_REQN          = 2'h2,
                                A_REQS          = 2'h3;

        parameter               R_NOP           = 2'h0,
                                R_SPC           = 2'h1,
                                R_REQN          = 2'h2,
                                R_REQS          = 2'h3;

        parameter               IDLE            = 2'h0,
                                BUSY            = 2'h1,
                                NONSEQ          = 2'h2,
                                SEQ             = 2'h3;

// *************************** I/O DECLARATIONS ********************************

        // AHB Interface
        input   [1:0]           HTRANS;
        input   [31:0]          HADDR;
        output                  HREADY;
        output  [31:0]          HRDATA;

        // Buffer Interface
        output                  oReq;
        input                   oGnt;
        output  [31:0]          oAddr;
        output                  oStrb;
        input                   oAck;
        output                  oFlush;
        input   [31:0]          oData;

        // Utility
        input                   reset;
        input                   clk;

// ************************** LOCAL DECLARATIONS *******************************

        reg     [1:0]           reqStat, reqStatD;
        reg     [1:0]           rdtStat, rdtStatD;

//      reg                     oReq;
        reg     [31:0]          oAddr;
//      reg                     oStrb;

// ****************************** MODULE BODY **********************************

// -----------------------------------------------------------------------------
// Requsest Path State Machine
always @(posedge clk)
        if (reset)
                reqStat         <= #1 A_NOP;
        else
                reqStat         <= #1 reqStatD;

always @(
        reqStat or
        HTRANS or
        HREADY
        ) begin

        reqStatD        = reqStat;

        if (HREADY) case (reqStat)
                A_NOP:  case (HTRANS)
                                NONSEQ: reqStatD        = A_REQN;
                                SEQ:    reqStatD        = A_REQS;
                        endcase

                A_REQN: case (HTRANS)
                                IDLE:   reqStatD        = A_NOP;
                                BUSY:   reqStatD        = A_NOP;
                                SEQ:    reqStatD        = A_REQS;
                        endcase

                A_REQS: case (HTRANS)
                                IDLE:   reqStatD        = A_NOP;
                                BUSY:   reqStatD        = A_NOP;
                                NONSEQ: reqStatD        = A_REQN;
                        endcase
        endcase
        else
                reqStatD        = A_NOP;
end

// -----------------------------------------------------------------------------
// Request Path Output
//
//always @(posedge clk)
//      if (reset)
//              oReq            <= #1 1'b0;
//      else
//              oReq            <= #1 (reqStatD == A_REQN)
//                                  | (reqStatD == A_REQS) & ~|HADDR[BLR+1:2];

assign oReq             = (reqStat == A_REQN)
                        | (reqStat == A_REQS) & ~|oAddr[BLR+1:2];

always @(posedge clk)
        if (reset)
                oAddr           <= #1 32'd0;
        else if (HREADY)
                oAddr           <= #1 HADDR;

// -----------------------------------------------------------------------------
// Read Data Path State Machine
always @(posedge clk)
        if (reset)
                rdtStat         <= #1 R_NOP;
        else
                rdtStat         <= #1 rdtStatD;

always @(
        rdtStat or
        HTRANS or
        HREADY
        ) begin

        rdtStatD        = rdtStat;

        if (HREADY) case (rdtStat)
                R_NOP:  case (HTRANS)
                                NONSEQ: rdtStatD        = R_REQN;
                                SEQ:    rdtStatD        = R_REQS;
                        endcase

                R_SPC:  case (HTRANS)
                                IDLE:   rdtStatD        = R_NOP;
                                NONSEQ: rdtStatD        = R_REQN;
                                SEQ:    rdtStatD        = R_REQS;
                        endcase

                R_REQN: case (HTRANS)
                                IDLE:   rdtStatD        = R_NOP;
                                BUSY:   rdtStatD        = R_SPC;
                                SEQ:    rdtStatD        = R_REQS;
                        endcase

                R_REQS: case (HTRANS)
                                IDLE:   rdtStatD        = R_NOP;
                                BUSY:   rdtStatD        = R_SPC;
                                NONSEQ: rdtStatD        = R_REQN;
                        endcase
        endcase
end

// -----------------------------------------------------------------------------
// Read Data Path Output
//
//always @(posedge clk)
//      if (reset)
//              oStrb           <= #1 1'b0;
//      else
//              oStrb           <= #1 (rdtStatD == R_REQN) | (rdtStatD == R_REQS);

assign oStrb            = (rdtStat == R_REQN) | (rdtStat == R_REQS);

assign oFlush           = (rdtStatD == R_NOP) | (rdtStatD == R_REQN)
                        | &oAddr[BLR+1:2];

// -----------------------------------------------------------------------------
// Through Control
assign HREADY           = (!oReq  | oGnt)
                        & (!oStrb | oAck);

assign HRDATA           = oData;

// ************************** FUNCTIONS and TASKS ******************************

endmodule

// *****************************************************************************
            




• Details are omitted but, condition variable may e even just 1. coding for that will be given as reference. output is almost same（Slight difference in the invalid interval due to flush signal and strb signal not being present.）Circuit magnitude will be very slightly bigger.


1 Condition state machine（2 conditions are reduced.）

/* **************************** MODULE PREAMBLE ********************************

        Copyright (c) 2012, ArchiTek
        This document constitutes confidential and proprietary information
        of ArchiTek. All rights reserved.
*/

// ***************************** MODULE HEADER *********************************

module busBridge_1 (
        HTRANS, HADDR, HREADY, HRDATA,
        oReq, oGnt, oAddr, oStrb, oAck, oFlush, oData,
        reset, clk
        );

// ************************ PARAMETER DECLARATIONS *****************************

        parameter               BLR             = 2;

        parameter               NOP             = 3'h0,
                                SPC             = 3'h1,
                                REQN            = 3'h4,
                                HOLDN           = 3'h5,
                                REQS            = 3'h6,
                                HOLDS           = 3'h7;

        parameter               IDLE            = 2'h0,
                                BUSY            = 2'h1,
                                NONSEQ          = 2'h2,
                                SEQ             = 2'h3;

// *************************** I/O DECLARATIONS ********************************

        // AHB Interface
        input   [1:0]           HTRANS;
        input   [31:0]          HADDR;
        output                  HREADY;
        output  [31:0]          HRDATA;

        // Buffer Interface
        output                  oReq;
        input                   oGnt;
        output  [31:0]          oAddr;
        output                  oStrb;
        input                   oAck;
        output                  oFlush;
        input   [31:0]          oData;

        // Utility
        input                   reset;
        input                   clk;

// ************************** LOCAL DECLARATIONS *******************************

        reg     [2:0]           stat, statD;

//      reg                     oReq;
        reg     [31:0]          oAddr;
//      reg                     oStrb;

// ****************************** MODULE BODY **********************************

// -----------------------------------------------------------------------------
// State Machine
always @(posedge clk)
        if (reset)
                stat            <= #1 NOP;
        else
                stat            <= #1 statD;

always @(
        stat or
        HTRANS or
        HREADY
        ) begin

        statD           = stat;

        case (stat)
                NOP:
                        if (HREADY)
                                case (HTRANS)
                                        NONSEQ: statD           = REQN;
                                endcase

                SPC:
                        if (HREADY)
                                case (HTRANS)
                                        IDLE:   statD           = NOP;
                                        NONSEQ: statD           = REQN;
                                        SEQ:    statD           = REQS;
                                endcase

                REQN:
                        if (HREADY)
                                case (HTRANS)
                                        IDLE:   statD           = NOP;
                                        BUSY:   statD           = SPC;
                                        SEQ:    statD           = REQS;
                                endcase
                        else
                                                statD           = HOLDN;

                HOLDN:
                        if (HREADY)
                                case (HTRANS)
                                        IDLE:   statD           = NOP;
                                        BUSY:   statD           = SPC;
                                        NONSEQ: statD           = REQN;
                                        SEQ:    statD           = REQS;
                                endcase

                REQS:
                        if (HREADY)
                                case (HTRANS)
                                        IDLE:   statD           = NOP;
                                        BUSY:   statD           = SPC;
                                        NONSEQ: statD           = REQN;
                                endcase
                        else
                                                statD           = HOLDS;

                HOLDS:
                        if (HREADY)
                                case (HTRANS)
                                        IDLE:   statD           = NOP;
                                        BUSY:   statD           = SPC;
                                        NONSEQ: statD           = REQN;
                                        SEQ:    statD           = REQS;
                                endcase
        endcase
end

// -----------------------------------------------------------------------------
// Requsest Path Output
//
//always @(posedge clk)
//      if (reset)
//              oReq            <= #1 1'b0;
//      else
//              oReq            <= #1 (statD == REQN)
//                                  | (statD == REQS) & ~|HADDR[BLR+1:2];

assign oReq             = (stat == REQN)
                        | (stat == REQS) & ~|oAddr[BLR+1:2];

always @(posedge clk)
        if (reset)
                oAddr           <= #1 32'd0;
        else if (HREADY)
                oAddr           <= #1 HADDR;

// -----------------------------------------------------------------------------
// Data Path Output
//
//always @(posedge clk)
//      if (reset)
//              oStrb           <= #1 1'b0;
//      else
//              oStrb           <= #1 (statD == REQN)
//                                  | (statD == HOLDN)
//                                  | (statD == REQS)
//                                  | (statD == HOLDS);

assign oStrb            = (stat == REQN)
                        | (stat == HOLDN)
                        | (stat == REQS)
                        | (stat == HOLDS);

assign oFlush           = (statD == NOP)
                        | (statD == REQN)
                        | &oAddr[BLR+1:2];

// -----------------------------------------------------------------------------
// Through Control
assign HREADY           = (!oReq  | oGnt)
                        & (!oStrb | oAck);

assign HRDATA           = oData;

// ************************** FUNCTIONS and TASKS ******************************

endmodule

// *****************************************************************************
            




• AHB Master, this bus bridge, and slave module combined test wave type sample is specified. Wording is small and difficult to read, transaction generated by AHB master is tranformed to burst access, required items are returned to AHB master.

• Cache Tag^[12]is a type of condition. When there is access, corresponding tag is extracted and after condition shift, is re-contained. Here against multiple conditions, will hypothesize whether resource sharing of state machine is effective or not.


• When number of conditions and control are same number N,（mutually exclusive relation）, then either state machine need to be N or, less than N which is M or, only 1.


• Cache access can be once per cycle generally, so M=1 is no problem. However, if there are multiple access then condition shift will have to be performed simulataneously. If multiple access are M then state machine also must be M.


• However, if M≠N then, multiplexer will be a problem.（not needed when M=N）. tried using a simple state machine but,（Refer to below sample）, when M exceeds a certain value then circuit is smaller for M=N. Which shows that decision to use or not use resource sharing for state machine can be judged based on the number of M.


• For reference, will not go into details as it is an image, when the below diagram state machine is M=N will show coding example. Condition stat is divided for each bit to match verilog HDL(IEEE1364-1995).



/* **************************** MODULE PREAMBLE ********************************

        Copyright (c) 2012, ArchiTek
        This document constitutes confidential and proprietary information
        of ArchiTek. All rights reserved.
*/

// ***************************** MODULE HEADER *********************************

module state (
        iPtr, iAct, iInit, iLoop,
        sPtr, sDone,
        aPtr, aDone,
        lPtr, lDone,
        cPtr, cDone, cFin,
        pPtr, pDone, pFin,
        stat0, stat1, stat2,
        reset, clk
        );

// ************************ PARAMETER DECLARATIONS *****************************

        parameter               CNR     = 6;            // Number Radix
        parameter               CN      = 1<<CNR;

// *************************** I/O DECLARATIONS ********************************

        // Input
        input   [CNR-1:0]       iPtr;
        input                   iAct;
        input                   iInit;
        input                   iLoop;

        // Selector
        input   [CNR-1:0]       sPtr;
        input                   sDone;

        // Arbiter
        input   [CNR-1:0]       aPtr;
        input                   aDone;

        // Loader
        input   [CNR-1:0]       lPtr;
        input                   lDone;

        // Command
        input   [CNR-1:0]       cPtr;
        input                   cDone;
        input                   cFin;

        // Pipeline
        input   [CNR-1:0]       pPtr;
        input                   pDone;
        input                   pFin;

        // State Output
        output  [CN-1:0]        stat0;
        output  [CN-1:0]        stat1;
        output  [CN-1:0]        stat2;

        // Utility
        input                   reset;
        input                   clk;

// ************************** LOCAL DECLARATIONS *******************************

        wire    [CN-1:0]        iActVec         = ('b1 << iPtr) & {CN{iAct}};
        wire    [CN-1:0]        iInitVec        = ('b1 << iPtr) & {CN{iInit}};
        wire    [CN-1:0]        iLoopVec        = ('b1 << iPtr) & {CN{iLoop}};
        wire    [CN-1:0]        sDoneVec        = ('b1 << sPtr) & {CN{sDone}};
        wire    [CN-1:0]        aDoneVec        = ('b1 << aPtr) & {CN{aDone}};
        wire    [CN-1:0]        lDoneVec        = ('b1 << lPtr) & {CN{lDone}};
        wire    [CN-1:0]        cDoneVec        = ('b1 << cPtr) & {CN{cDone}};
        wire    [CN-1:0]        cFinVec         = ('b1 << cPtr) & {CN{cFin}};
        wire    [CN-1:0]        pDoneVec        = ('b1 << pPtr) & {CN{pDone}};
        wire    [CN-1:0]        pFinVec         = ('b1 << pPtr) & {CN{pFin}};

        reg     [CN-1:0]        stat0,  stat1,  stat2;
        reg     [CN-1:0]        stat0D, stat1D, stat2D;

        integer                 i;

// ****************************** MODULE BODY **********************************

// -----------------------------------------------------------------------------
// State Machine
parameter       IDLE    = 3'h0,
                LOCK    = 3'h2,
                FLUSH   = 3'h3,
                PROG    = 3'h4,
                LDRQ    = 3'h6,
                LDDO    = 3'h7;

always @(posedge clk) for (i=0; i<CN; i=i+1)
        if (reset)
                {stat0[i], stat1[i], stat2[i]}
                                <= #1 IDLE;
        else
                {stat0[i], stat1[i], stat2[i]}
                                <= #1 {stat0D[i], stat1D[i], stat2D[i]};

always @(
        stat0 or stat1 or stat2 or
        iActVec or iInitVec or iLoopVec or
        sDoneVec or
        aDoneVec or
        lDoneVec or
        cDoneVec or cFinVec or
        pDoneVec or pFinVec
        ) for (i=0; i<CN; i=i+1) begin

        {stat0D[i], stat1D[i], stat2D[i]}
                        = {stat0[i], stat1[i], stat2[i]};

        case ({stat0[i], stat1[i], stat2[i]})
                IDLE:   if (iActVec[i])
                case (iInitVec[i])
                        1'b0:   {stat0D[i], stat1D[i], stat2D[i]}       = PROG;
                        1'b1:   {stat0D[i], stat1D[i], stat2D[i]}       = LDRQ;
                endcase

                LDRQ:   if (sDoneVec[i])
                                {stat0D[i], stat1D[i], stat2D[i]}       = LDDO;

                LDDO:   if (lDoneVec[i])
                                {stat0D[i], stat1D[i], stat2D[i]}       = PROG;

                PROG:   if (aDoneVec[i])
                                {stat0D[i], stat1D[i], stat2D[i]}       = LOCK;

                LOCK:   if (cDoneVec[i])
                casex ({cFinVec[i], iActVec[i]})
                        2'b00:  {stat0D[i], stat1D[i], stat2D[i]}       = IDLE;
                        2'b01:  {stat0D[i], stat1D[i], stat2D[i]}       = PROG;
                        2'b1x:  {stat0D[i], stat1D[i], stat2D[i]}       = FLUSH;
                endcase

                FLUSH:  if (pDoneVec[i] & pFinVec[i])
                casex ({iLoopVec[i], iInitVec[i], iActVec[i]})
                        3'b0xx,
                        3'b1x0: {stat0D[i], stat1D[i], stat2D[i]}       = IDLE;
                        3'b101: {stat0D[i], stat1D[i], stat2D[i]}       = PROG;
                        3'b111: {stat0D[i], stat1D[i], stat2D[i]}       = LDRQ;
                endcase
        endcase
end

// ************************** FUNCTIONS and TASKS ******************************

endmodule

// *****************************************************************************
            

Logical Circuit Design > Technic > State Machine    Next page（Gated Clock）    TOP of this page ▲

[1]
Interpretation is vague due to specifications. For example the action taken against an error.

For convenience resetting, insertion of sequence for restart, keep pending and shift control to software are various examples.

Actually will affect system design also, there isnt anything more inconvenient then sequence determined by specification.

[2]
There is theory of combination, but cannot research what is best for circuit design.

When combining, number of conditions upper limit would be 32. From experience, when mutually conditions overlap, then complexity will increase by a factor of 2 to number of conditions. Based on this reasoning, condition on the right side of the diagram is simple.（7² > 2²+3²+4²）。

State machine for analyzing header of JPEG and MPEG will have no problems even with 100 states. There is less mutual shifts also, and as it is specified, can be stable (will doubt it though)

Incidentally, when composing 100 states, circuit and logical steps are smaller than expected.

[3]
Small scale state machine is mapped locally, so even when logical stapes are morem can be smaller.

Actually have designed a state machine with restricted timing, One hot improvement was small. First must tidy the value of state before retrying.

[4]
Simply an example. Having a base for thinking, thought process will be smoother. In this case it is output signal but, can be centered around input signal or defined state.

The former is an extreme example but is an example of program counter of processor.

Further the latter isDDR control which can be seen in example of memory condition of DDR.

[5]
Asynchronous here does not mean difference in clock frequency. It means state is independent, and operates without mutual relation. Same as asynchronous used in software control.

[6]
Even as safety measures are taken, it is easy to overlook bugs. Unmeasured states to check using assertion,（sufficient to embed display command）and try to resolve bugs.

[7]
Details are edgy but, due to special characteristics of AHB, combining will make control simpler. Actually is usual to divide into master and slave when using so take care.

Further, AHB is a synchronized protocol for Request control and Data control, can be thought that it is already connected by input signal. Hoever because of this performance cannot be achieved, here AXI is defined like bus.

[8]
Here when the omitted HBRUST signal is seen, Can determine the specified burst length. However, AHB specifications allow for abort while access. Burst length needs to check this abort. Abort can be seen when HTRANS="SEQ" is "IDLE", "NONSEQ".

[9]
Wise person may realize a shortcoming. When access is aborted with "IDLE" or "NONSEQ" after HTRANS="BUSY", flus signal will not output together with strb signal. Want to assert flush signal at the time of "BUSY", but cannot determine whather access has been aborted with "BUSY"

When properly implemented, HREADY is Stalled so that dummy strb + flush signal asserted condition can be added, and will be complex

Do not think that HTRANS = "BUSY" immediately before aborting access by master of AHB...

[10]
It is not One hot, if each bit is orthogonal, then can realize reduction of logical steps and circuit size between FF.

Although when referencing state, when creating logic depending on specific bits, wil not be able to adjust when later increasing states or changing. Would be better to code using state names as much as possible（Synthesis tool will automatically compress circuit.）

[11]
This coding method will have less condition omissions. However, depending on the RTL checker may get message "no default for case()!" causing confusion. If worried, then code a default statement for case() or a full condition code.

[12]
If direct map type or set associative type, can determine state only with address, multiplexer is not required.