Latency(CLK) | 0 |
module gearIT(iData, iCnt, iVld, iStall, oData, oVld, oStall, reset, clk);
parameter W = 32;
parameter D = 4;
input [W-1:0] iData;
input [D-1:0] iCnt; // Count Number - 1
input iVld;
output iStall;
output [W-1:0] oData;
output oVld;
input oStall;
input reset;
input clk;
wire oAlloc = oVld & !oStall;
reg [D-1:0] cnt; // Incrementer
wire fin = oAlloc & (cnt == iCnt);
always @(posedge clk)
if (reset | fin)
cnt <= #1 {D{1'b0}};
else
cnt <= #1 cnt + oAlloc;
assign iStall = iVld & !fin;
assign oData = xxxFunc(iData);
assign oVld = iVld;
function [W-1:0] xxxFunc;
input [W-1:0] data;
xxxFunc = data;
endfunction
endmodule
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