IP core

We offer a variety of IP cores, including IP with unique and original functions.

Below is an introduction to our main IP cores and examples of IP-based designs.

１．Sample Design Hierarchy

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  • 「Overall」：From ideas to specification and design
  • 「Engine」：Design and customize engines using standard IPs
  • 「Integration」：Optimize and streamline for performance and cost

２．IP families

(１) Platform IP

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(２) Image Processing IP

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※ Command list (parameters) is auto-fetched, with no pipeline bubbles between tasks
※ Best used with the pss scheduler, but also works standalone without issues

(３) Signal Processing IP

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※ Command list (parameters) is auto-fetched, with no pipeline bubbles between tasks
※ Best used with the pss scheduler, but also works standalone without issues

(４) AI・Processor IP

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(５) I/O IP

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(６) General-purpose IP

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３．Design examples utilizing IP

Example１：General-Purpose I/O Processing Chip (Homogeneous Type)

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An I/O processing chip with low latency, controlled by software

Example２：Edge AI / Image Processing Chip (Heterogeneous Type)

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A high-performance, low-power chip integrating a dedicated engine and a general-purpose processor

Example３：Programmable Radar Chip (Hybrid Homogeneous/Heterogeneous Architecture)

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A high-performance chip capable of arbitrary combinations of high-speed frequency conversion and signal processing