IP core
We offer a variety of IP cores, including IP with unique and original functions.
Below is an introduction to our main IP cores and examples of IP-based designs.
１．Sample Design Hierarchy
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「Overall」：From ideas to specification and design
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「Engine」：Design and customize engines using standard IPs
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「Integration」：Optimize and streamline for performance and cost
２．IP families
(１) Platform IP
mcxc
pss
(２) Image Processing IP
※ Command list (parameters) is auto-fetched, with no pipeline bubbles between tasks
※ Best used with the pss scheduler, but also works standalone without issues
frComp
frLabel
frBlt
(３) Signal Processing IP
※ Command list (parameters) is auto-fetched, with no pipeline bubbles between tasks
※ Best used with the pss scheduler, but also works standalone without issues
sigFFT
sigComp
sigSort
sigImp
(４) AI・Processor IP
※Command list (parameters) is auto-fetched, with no pipeline bubbles between tasks
※ Best used with the pss scheduler, but also functions independently without issues
mmap
kp
(５) I/O IP
(６) General-purpose IP
３．Design examples utilizing IP
Example１：General-Purpose I/O Processing Chip (Homogeneous Type)
An I/O processing chip with low latency, controlled by software
Example２：Edge AI / Image Processing Chip (Heterogeneous Type)
A high-performance, low-power chip integrating a dedicated engine and a general-purpose processor
Example３：Programmable Radar Chip (Hybrid Homogeneous/Heterogeneous Architecture)
A high-performance chip capable of arbitrary combinations of high-speed frequency conversion and signal processing
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