Preface
- Generally used single port SRAM and 2 port SRAM model code.
- Write is written at assert timing, Read is output with 1 clock delay. In case of 2 port SRAM, even if R/W address is overlapped, it will not be an unknown but will access memory as specified.
Single port SRAM
/* **************************** MODULE PREAMBLE ********************************
Copyright (c) 2012, ArchiTek
This document constitutes confidential and proprietary information
of ArchiTek. All rights reserved.
*/
// ***************************** MODULE HEADER *********************************
module singleSRAM (
CE, RW, AD, WD, RD, CK
);
// ************************ PARAMETER DECLARATIONS *****************************
parameter W = 32;
parameter DR = 9;
parameter M = W/8;
parameter D = 1<<DR;
// ***************************** I/O DECLARATIONS ******************************
input CE;
input RW;
input [DR-1:0] AD;
input [W-1:0] WD;
output [W-1:0] RD;
input CK;
// ************************** LOCAL DECLARATIONS *******************************
reg [W-1:0] mem[0:D-1];
reg [DR-1:0] la;
// ******************************** MODULE BODY ********************************
always @(posedge CK)
if (CE & !RW)
mem[AD] <= #1 WD;
always @(posedge CK)
if (CE)
la <= #1 AD;
assign RD = mem[la];
endmodule
// **************************** FUNCTIONS and TASKS ****************************
endmodule
// *****************************************************************************
2ポートSRAM
/* **************************** MODULE PREAMBLE ********************************
Copyright (c) 2012, ArchiTek
This document constitutes confidential and proprietary information
of ArchiTek. All rights reserved.
*/
// ***************************** MODULE HEADER *********************************
module dualSRAM (
WE, WA, WD, RE, RA, RD, CK
);
// ************************ PARAMETER DECLARATIONS *****************************
parameter W = 32;
parameter DR = 9;
parameter M = W/8;
parameter D = 1<<DR;
// ***************************** I/O DECLARATIONS ******************************
input WE;
input [DR-1:0] WA;
input [W-1:0] WD;
input RE;
input [DR-1:0] RA;
output [W-1:0] RD;
input CK;
// ************************** LOCAL DECLARATIONS *******************************
reg [W-1:0] mem[0:D-1];
reg [DR-1:0] la;
// ******************************** MODULE BODY ********************************
always @(posedge CK)
if (WE)
mem[WA] <= #1 WD;
always @(posedge CK)
if (RE)
la <= #1 RA;
assign RD = mem[la];
endmodule
// **************************** FUNCTIONS and TASKS ****************************
endmodule
// *****************************************************************************
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