Divide processing into packets to optimally start hardware processing.

• By showing the hardware to be infinite, remove unified control of software.
• If following simple interface specifications, simple connection is possible (plugin).
• Simple software control independent of hardware is possible.

Using just parts and connection definition file, can implement customized engine.

• By using micro packet technology, can simultaneously define an infinite number of engines.
• The more that the basic components are variable the more they can be shared and circuit area can be reduced.
• Using inter connect technology with cache, can connect engines with low power, low memory resources.

Execution of any code including high level functions without penalty.

• New concept compact high performance GPU architecture.
• Executes multiple step pipeline trigonometric functions also in 1 cycle throughput.
• Programming is simple as even if there is data dependency, there is no penalty.
• Less control of number of processors or operator types so simple to change.
• Image processing GPU (P-Cube) utilizes this technology.

Reduce load on external memory by using wide bandwidth multi-bank cache.

• Number of banks and various parameters are variable and can select various options such as MMU or bandwidth restrictions so can be used in a variety of solutions.
• Unifying a distributed internal SRAM or optimal control of SDRAM (usage 90%, low latency) is possible.
• This technology is used in general purpose memory controller IP (E=mc²).

Careful selection/polishing of image processing components and architecture technology.

• IPE is a compact, low power consumption, low latency in hardware and flexibility in software programmable image processing IP.
• IPE offers 3 merits (flexibility, realtime & low power consumption, and simple programming) which was not seen previously.
• Offers an embedded solution flexible for widening intelligent image sensing uses.

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