Ensure bandwidth of parallel bus
- High performance interconnect fills up the gap between large volume characteristics required by memory (external memory) and large bandwidth characteristics (various engines).
- Bus requisitions by equally handling multi bank cache reduces the burden on external memory greatly.
- Exhibits power in local and bus simultaneous access, realizing a low latency high throughput memory system.
- Also by gathering internal SRAM and cache, rationalization of the entire system can be realized.
Low power consumption technology
- Each block is monitored at clock unit, clock control is inclusive of SDRAM and miniaturization of operational circuit is realized.
- Random access is bundled at burst access of cache so external memory is not used unnecessarily.
- If the access is local, due to the effect of cache, external memory is not much used.
Customization potential for a variety of scenes
- By using 1 template, and by just adding/removing required components, requisite interconnect can be assembled.
- Especially for cache, number of ways or capacity is also scalable so system tuning is required.
